The present invention relates generally to the field of data communications, and more particularly, to the field of serial communications bus controllers and microcontrollers that incorporate the same.
CAN (Control Area Network) is an industry-standard, two-wire serial communications bus that is widely used in automotive and industrial control applications, as well as in medical devices, avionics, office automation equipment, consumer appliances, and many other products and applications. CAN controllers are currently available either as stand-alone devices adapted to interface with a microcontroller or as circuitry integrated into or modules embedded in a microcontroller chip. Since 1986, CAN users (software programmers) have developed numerous high-level CAN Application Layers (CALs) which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format, and adhering to the CAN specification. CALs have heretofore been implemented primarily in software, with very little hardware CAL support. Consequently, CALs have heretofore required a great deal of host CPU intervention, thereby increasing the processing overhead and diminishing the performance of the host CPU.
Thus, there is a need in the art for a CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance. One of the most demanding and CPU resource-intensive CAL functions is message management, which entails the handling, storage, and processing of incoming CAL/CAN messages received over the CAN serial communications bus and/or outgoing CAL/CAN messages transmitted over the CAN serial communications bus. CAL protocols, such as DeviceNet, CANopen, and OSEK, deliver long messages distributed over many CAN frames, which methodology is sometimes referred to as xe2x80x9cfragmentedxe2x80x9d or xe2x80x9csegmentedxe2x80x9d messaging. The process of assembling such fragmented, multi-frame messages has heretofore required a great deal of host CPU intervention. In particular, CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data, in order to facilitate the assembly of the message fragments or segments into complete messages.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance.
The assignee of the present invention has recently developed a new microcontroller product, designated xe2x80x9cXA-C3xe2x80x9d, that fulfills this need in the art. The XA-C3 is the newest member of the Philips XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. It is believed that the XA-C3 is the first chip that features hardware CAL support.
The XA-C3 is a CMOS 16-bit CAL/CAN 2.0B microcontroller that incorporates a number of different inventions, including the present invention. These inventions include novel techniques and hardware for filtering, buffering, handling, and processing CAL/CAN messages, including the automatic assembly of multi-frame fragmented messages with minimal CPU intervention, as well as for managing the storage and retrieval of the message data, and the memory resources utilized therefor.
The present invention relates to a CAN microcontroller that utilizes a dedicated RAM memory space, e.g., dedicated RAM modules, to store setup and configuration information (command/control fields) for each of a plurality of message objects supported by the CAN microcontroller. A significant amount of die area is conserved by implementing these memory-mapped registers in RAM modules as opposed to conventional flip-flop based registers. The use of conventional flip-flop based registers also would result in increased power consumption and radiated noise due to tremendously increased parasitic loading on clock lines, as well as entailing significant additional costs. Thus, the present invention achieves enhanced performance, lower cost, and smaller size relative to the presently available technology.
The present invention encompasses a CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, a CAN/CAL module that processes incoming messages, and a data memory space. The data memory space includes a plurality of message buffers associated with respective ones of the message objects, and a dedicated RAM memory space that contains a plurality of memory-mapped registers associated with each of the message objects. The plurality of memory-mapped registers associated with each message object correspond to respective command/control fields for facilitating configuration and setup of that message object. Each of the memory-mapped registers is mapped to a respective storage location within the dedicated RAM memory space.
In one embodiment, the dedicated RAM memory space encompasses a plurality of separate RAM modules, each RAM module being dedicated to a respective one of the command/control fields. The memory-mapped registers corresponding to a respective one of the command/control fields are located in respective, designated addressable memory storage locations within the separate RAM module dedicated to that command/control field, with a different addressable memory storage location being designated for each respective one of the message objects. In one particular implementation, all of the memory-mapped registers corresponding to a respective one of the command/control fields are located in a respective one of the separate RAM modules dedicated to that command/control field.
In a presently preferred embodiment, the CAN microcontroller supports a number n of message objects each having a number m of associated memory mapped registers corresponding to m respective command/control fields, with n different addressable storage locations being designated in each separate RAM module, one for each of the n respective message objects. In this embodiment, the dedicated RAM memory space encompasses m separate RAM modules, each of the separate RAM modules corresponding to a respective one of the m command/control fields.
Preferably, the memory-mapped registers appear as special function registers to the CAN applications that run on the processor core, but are accessed as RAM by hardware within the CAN microcontroller.